1. Technical Field
The present invention relates to a self-excited inverter circuit which, using a high voltage drive output generated in a secondary coil when two FETs with their respective drains connected to a primary coil are turned on alternately, drives and turns on a discharge tube serving as the light source of the back light of a liquid crystal panel and, more specifically, the invention relates to a self-excited inverter circuit arranged such that two FETs are formed in a single package.
2. Related Art
As a circuit for driving a cold cathode tube serving as the light source of the backlight of a liquid crystal display device having a size of about 15 inches, there is used such a self-excited inverter circuit as shown in FIG. 2. That is, in this inverter circuit, when a pair of N-channel FETs (which are hereinafter referred to as FETs simply) 11, 12 are turned on alternately, there is generated a high voltage drive output in a secondary coil L2, and the thus generated high voltage drive output is used to drive and turn on a cold cathode tube 4. Also, for the FETs 11, 12, there is used an element (for example, a PW-MOLD type element) formed in a package which can be mounted on a soldered surface and the respective drains of the FETs 11, 12, as shown in FIG. 4, are connected through patterns 81, 82 to a primary coil L1 (in a package 91, there is formed the FET 11; and, in a package 92, there is formed the FET 12).
As described above, the FET 11 and FET 12 are different elements which are respectively formed in mutually different packages. Therefore, the gate threshold voltage of the FET 11 and the gate threshold voltage of the FET 12 can differ greatly from each other due to variations in production. In this case, there is generated a relatively large difference between the turn-on period of the FET 11 and the turn-on period of the FET 12. And, in the FET the turn-on period of which is long, the heat value thereof is larger than that of the other FET and thus the element temperature thereof is higher. As a result of this, on the side where the element temperature is higher, the gate threshold value voltage becomes low and thus the turn-on period thereof increases further. That is, between the two FETs, a difference in the turn-on periods thereof increases. And, when the difference in the turn-on periods between the two FETs increases and thus imbalance between the switching operations increases, the wave form of the high voltage drive output for driving and turning on the cold cathode tube 4 is distorted. This incurs an inconvenience that a given level of luminance cannot be obtained, or the like.
In view of the above circumstances, there has been proposed a technique to be disclosed below (which is herein referred to as a first conventional technique). That is, in this technique, bias voltages to be applied to the gates of switching FETs are generated using a voltage divider circuit. And, the bias voltages generated in the voltage divider circuit are guided to the respective gates of the switching FETs through resistors so provided as to correspond to their respective switching FETs. Also, there are provided a diode with its cathode connected to the drain of one FET and its anode connected to the gate of the other FET, a diode with its cathode connected to the drain of the other FET and its anode connected to the gate of one FET. Therefore, on the side of the FET to be turned on, a voltage to be applied to the gate thereof is automatically controlled so as to provide a proper value in the vicinity of the threshold value. That is, even when the gate threshold value voltage varies, the voltage to be applied to the gate is controlled so as to correct such variation. As a result of this, there can be prevented the occurrence of a situation that the turn-on period of one FET is longer than that of the other FET, which can in turn prevent the occurrence of the distorted wave form of the high voltage drive output (for example, see JP-A-11-235052).
Also, there has been proposed another technique to be discussed below (which is herein referred to as a second technique). That is, this technique is applied to a half bridge type inverter circuit. Specifically, this technique is applied to a circuit which, as switching elements, uses a pair of elements composed of a complementary combination of an N-channel FET and a P-channel FET. And, with regard to the two FETs, namely, the N-channel FET and P-channel FET, there is employed a structure in which they are formed in the same package. Also, as for a pair of Zener diodes to be connected between the gate of one complementary FET and the source of the other complementary FET as well, there is used a structure in which the pair of Zener diodes are formed in the same package. As a result of this, the area of the circuit necessary for mounting the elements can be reduced, thereby being able to enhance the mounting efficiency of the elements (for example, see JP-A-2003-317988).